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[HandshakeOptimizeBitwidths] Fix bitwidth reduction of sign-extended or (#778)
The transfer function of `ori` currently always uses zero-extension. This is incorrect when bitwidth reduction occurs and the operands were originally sign-extended as the upper bits that might have previously been ones, would now be 0 through the zero-extension. This PR fixes that by adjusting the transfer function to sign-extend when one of its inputs is sign-extended. In the case that one operand is zero-extended, the computation additionally needs to be performed with an extra bit to not quasi sign-extend both operands. Alive 2 proofs: https://alive2.llvm.org/ce/z/Rze2eL https://alive2.llvm.org/ce/z/NJAWFy https://alive2.llvm.org/ce/z/amxV5R Fixes #765 Depends on #766
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Lines changed: 86 additions & 4 deletions

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‎lib/Transforms/HandshakeOptimizeBitwidths.cpp‎

Lines changed: 30 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -366,14 +366,22 @@ struct ExtWidth {
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/// If needed, swaps the operands such that 'rhs' contains the larger extension
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/// type.
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/// This allows eliminating symmetrical cases in commutative operations.
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static void ignoreCommutativity(ExtWidth &lhs, ExtWidth &rhs) {
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/// Users are allowed to assume that 'rhs.extType >= lhs.extType'.
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/// The cases that need to be handled are then only:
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/// * NONE, NONE
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/// * NONE, LOGICAL
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/// * NONE, ARITHMETIC
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/// * LOGICAL, LOGICAL
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/// * LOGICAL, ARITHMETIC
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/// * ARITHMETIC, ARITHMETIC
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static void canonicalizeCommutativeExtensionType(ExtWidth &lhs, ExtWidth &rhs) {
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if (lhs.extType > rhs.extType)
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std::swap(lhs, rhs);
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}
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/// Transfer function for add/sub operations or alike.
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static ExtWidth addWidth(ExtWidth lhs, ExtWidth rhs) {
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ignoreCommutativity(lhs, rhs);
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canonicalizeCommutativeExtensionType(lhs, rhs);
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if (rhs.extType <= ExtType::LOGICAL)
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return {ExtType::LOGICAL, std::max(lhs.bitWidth, rhs.bitWidth) + 1};
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@@ -393,7 +401,7 @@ static ExtWidth divWidth(ExtWidth lhs, ExtWidth _) {
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/// Transfer function for and operations or alike.
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static ExtWidth andWidth(ExtWidth lhs, ExtWidth rhs) {
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ignoreCommutativity(lhs, rhs);
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canonicalizeCommutativeExtensionType(lhs, rhs);
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// Given two operands such as "a = 01, b = 101":
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// If both operands are zero-extended or not extended at all, then the
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// effective bitwidth is whichever is smaller since 1) any bits beyond
@@ -424,7 +432,25 @@ static ExtWidth andWidth(ExtWidth lhs, ExtWidth rhs) {
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/// Transfer function for or/xor operations or alike.
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static ExtWidth orWidth(ExtWidth lhs, ExtWidth rhs) {
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return {ExtType::LOGICAL, std::max(lhs.bitWidth, rhs.bitWidth)};
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canonicalizeCommutativeExtensionType(lhs, rhs);
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if (rhs.extType <= ExtType::LOGICAL)
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return {ExtType::LOGICAL, std::max(lhs.bitWidth, rhs.bitWidth)};
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// rhs guaranteed to be at least arithmetic from here on.
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// Since rhs was sign-extended the result to continue extending with 1s in the
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// case rhs extends with 1s.
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// However, if lhs is zero-extended and the larger bitwidth, we need to add
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// one extra bit to the result such the result isn't sign-extended using the
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// sign-bit of lhs.
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// Example: lhs = zext(101) to i32, rhs = sext(01) to i32.
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// We must perform the OR using 3 bits at the very least. Performing it
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// with 3 bits would be wrong however, since sext(OR 101, sext(01) to i3)
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// would extend with 1s, merely due to the bitwidth reduction.
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// The extra bit prevents this behavior.
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if (lhs.extType == ExtType::LOGICAL && lhs.bitWidth > rhs.bitWidth)
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return {ExtType::ARITHMETIC, 1 + lhs.bitWidth};
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return {ExtType::ARITHMETIC, std::max(lhs.bitWidth, rhs.bitWidth)};
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}
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//===----------------------------------------------------------------------===//

‎test/Transforms/HandshakeOptimizeBitwidths/gh765.mlir‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
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// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py
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// RUN: dynamatic-opt --handshake-optimize-bitwidths --remove-operation-names %s --split-input-file | FileCheck %s
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// CHECK-LABEL: handshake.func @test_and_sext_sext(
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// CHECK-SAME: %[[VAL_0:.*]]: !handshake.channel<i1>,
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// CHECK-SAME: %[[VAL_1:.*]]: !handshake.channel<i16>,
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// CHECK-SAME: %[[VAL_2:.*]]: !handshake.control<>, ...) -> (!handshake.channel<i32>, !handshake.control<>) attributes {argNames = ["arg0", "arg1", "start"], resNames = ["out0", "end"]} {
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// CHECK: %[[VAL_3:.*]] = extsi %[[VAL_0]] {handshake.bb = 0 : ui32} : <i1> to <i16>
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// CHECK: %[[VAL_4:.*]] = ori %[[VAL_3]], %[[VAL_1]] {handshake.bb = 0 : ui32} : <i16>
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// CHECK: %[[VAL_5:.*]] = extsi %[[VAL_4]] : <i16> to <i32>
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// CHECK: end {handshake.bb = 0 : ui32} %[[VAL_5]], %[[VAL_2]] : <i32>, <>
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// CHECK: }
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handshake.func @test_and_sext_sext(%arg0: !handshake.channel<i1>, %arg1: !handshake.channel<i16>, %arg2: !handshake.control<>, ...) -> (!handshake.channel<i32>, !handshake.control<>) attributes {argNames = ["arg0", "arg1", "start"], resNames = ["out0", "end"]} {
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%0 = extsi %arg0 {handshake.bb = 0 : ui32, handshake.name = "extsi0"} : <i1> to <i32>
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%1 = extsi %arg1 {handshake.bb = 0 : ui32, handshake.name = "extsi1"} : <i16> to <i32>
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%2 = ori %0, %1 {handshake.bb = 0 : ui32, handshake.name = "andi0"} : <i32>
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end {handshake.bb = 0 : ui32, handshake.name = "end0"} %2, %arg2 : <i32>, <>
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}
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// -----
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// CHECK-LABEL: handshake.func @test_and_sext_zext(
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// CHECK-SAME: %[[VAL_0:.*]]: !handshake.channel<i1>,
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// CHECK-SAME: %[[VAL_1:.*]]: !handshake.channel<i16>,
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// CHECK-SAME: %[[VAL_2:.*]]: !handshake.control<>, ...) -> (!handshake.channel<i32>, !handshake.control<>) attributes {argNames = ["arg0", "arg1", "start"], resNames = ["out0", "end"]} {
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// CHECK: %[[VAL_3:.*]] = extui %[[VAL_1]] {handshake.bb = 0 : ui32} : <i16> to <i17>
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// CHECK: %[[VAL_4:.*]] = extsi %[[VAL_0]] {handshake.bb = 0 : ui32} : <i1> to <i17>
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// CHECK: %[[VAL_5:.*]] = ori %[[VAL_4]], %[[VAL_3]] {handshake.bb = 0 : ui32} : <i17>
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// CHECK: %[[VAL_6:.*]] = extsi %[[VAL_5]] : <i17> to <i32>
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// CHECK: end {handshake.bb = 0 : ui32} %[[VAL_6]], %[[VAL_2]] : <i32>, <>
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// CHECK: }
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handshake.func @test_and_sext_zext(%arg0: !handshake.channel<i1>, %arg1: !handshake.channel<i16>, %arg2: !handshake.control<>, ...) -> (!handshake.channel<i32>, !handshake.control<>) attributes {argNames = ["arg0", "arg1", "start"], resNames = ["out0", "end"]} {
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%0 = extsi %arg0 {handshake.bb = 0 : ui32, handshake.name = "extsi0"} : <i1> to <i32>
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%1 = extui %arg1 {handshake.bb = 0 : ui32, handshake.name = "extsi1"} : <i16> to <i32>
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%2 = ori %0, %1 {handshake.bb = 0 : ui32, handshake.name = "andi0"} : <i32>
36+
end {handshake.bb = 0 : ui32, handshake.name = "end0"} %2, %arg2 : <i32>, <>
37+
}
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40+
// -----
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42+
// CHECK-LABEL: handshake.func @test_and_zext_sext(
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// CHECK-SAME: %[[VAL_0:.*]]: !handshake.channel<i1>,
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// CHECK-SAME: %[[VAL_1:.*]]: !handshake.channel<i16>,
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// CHECK-SAME: %[[VAL_2:.*]]: !handshake.control<>, ...) -> (!handshake.channel<i32>, !handshake.control<>) attributes {argNames = ["arg0", "arg1", "start"], resNames = ["out0", "end"]} {
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// CHECK: %[[VAL_3:.*]] = extui %[[VAL_0]] {handshake.bb = 0 : ui32} : <i1> to <i16>
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// CHECK: %[[VAL_4:.*]] = ori %[[VAL_3]], %[[VAL_1]] {handshake.bb = 0 : ui32} : <i16>
48+
// CHECK: %[[VAL_5:.*]] = extsi %[[VAL_4]] : <i16> to <i32>
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// CHECK: end {handshake.bb = 0 : ui32} %[[VAL_5]], %[[VAL_2]] : <i32>, <>
50+
// CHECK: }
51+
handshake.func @test_and_zext_sext(%arg0: !handshake.channel<i1>, %arg1: !handshake.channel<i16>, %arg2: !handshake.control<>, ...) -> (!handshake.channel<i32>, !handshake.control<>) attributes {argNames = ["arg0", "arg1", "start"], resNames = ["out0", "end"]} {
52+
%0 = extui %arg0 {handshake.bb = 0 : ui32, handshake.name = "extsi0"} : <i1> to <i32>
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%1 = extsi %arg1 {handshake.bb = 0 : ui32, handshake.name = "extsi1"} : <i16> to <i32>
54+
%2 = ori %0, %1 {handshake.bb = 0 : ui32, handshake.name = "andi0"} : <i32>
55+
end {handshake.bb = 0 : ui32, handshake.name = "end0"} %2, %arg2 : <i32>, <>
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}

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