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Sean V Kelleygregkh
Sean V Kelley
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gregkh
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PCI: Add boot interrupt quirk mechanism for Xeon chipsets
commit b88bf6c upstream. The following was observed by Kar Hin Ong with RT patchset: Backtrace: irq 19: nobody cared (try booting with the "irqpoll" option) CPU: 0 PID: 3329 Comm: irq/34-nipalk Tainted:4.14.87-rt49 #1 Hardware name: National Instruments NI PXIe-8880/NI PXIe-8880, BIOS 2.1.5f1 01/09/2020 Call Trace: <IRQ> ? dump_stack+0x46/0x5e ? __report_bad_irq+0x2e/0xb0 ? note_interrupt+0x242/0x290 ? nNIKAL100_memoryRead16+0x8/0x10 [nikal] ? handle_irq_event_percpu+0x55/0x70 ? handle_irq_event+0x4f/0x80 ? handle_fasteoi_irq+0x81/0x180 ? handle_irq+0x1c/0x30 ? do_IRQ+0x41/0xd0 ? common_interrupt+0x84/0x84 </IRQ> ... handlers: [<ffffffffb3297200>] irq_default_primary_handler threaded [<ffffffffb3669180>] usb_hcd_irq Disabling IRQ #19 The problem being that this device is triggering boot interrupts due to threaded interrupt handling and masking of the IO-APIC. These boot interrupts are then forwarded on to the legacy PCH's PIRQ lines where there is no handler present for the device. Whenever a PCI device fires interrupt (INTx) to Pin 20 of IOAPIC 2 (GSI 44), the kernel receives two interrupts: 1. Interrupt from Pin 20 of IOAPIC 2 -> Expected 2. Interrupt from Pin 19 of IOAPIC 1 -> UNEXPECTED Quirks for disabling boot interrupts (preferred) or rerouting the handler exist but do not address these Xeon chipsets' mechanism: https://lore.kernel.org/lkml/12131949181903-git-send-email-sassmann@suse.de/ Add a new mechanism via PCI CFG for those chipsets supporting CIPINTRC register's dis_intx_rout2ich bit. Link: https://lore.kernel.org/r/20200220192930.64820-2-sean.v.kelley@linux.intel.com Reported-by: Kar Hin Ong <kar.hin.ong@ni.com> Tested-by: Kar Hin Ong <kar.hin.ong@ni.com> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Lines changed: 73 additions & 7 deletions

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‎drivers/pci/quirks.c‎

Lines changed: 73 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1970,26 +1970,92 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk
19701970
/*
19711971
* IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
19721972
* 300641-004US, section 5.7.3.
1973+
*
1974+
* Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1975+
* Core IO on Xeon E5 v2, see Intel order no 329188-003.
1976+
* Core IO on Xeon E7 v2, see Intel order no 329595-002.
1977+
* Core IO on Xeon E5 v3, see Intel order no 330784-003.
1978+
* Core IO on Xeon E7 v3, see Intel order no 332315-001US.
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* Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1980+
* Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1981+
* Core IO on Xeon D-1500, see Intel order no 332051-001.
1982+
* Core IO on Xeon Scalable, see Intel order no 610950.
19731983
*/
1974-
#define INTEL_6300_IOAPIC_ABAR 0x40
1984+
#define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
19751985
#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
19761986

1987+
#define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
1988+
#define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
1989+
19771990
static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
19781991
{
19791992
u16 pci_config_word;
1993+
u32 pci_config_dword;
19801994

19811995
if (noioapicquirk)
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return;
19831997

1984-
pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1985-
pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1986-
pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1987-
1998+
switch (dev->device) {
1999+
case PCI_DEVICE_ID_INTEL_ESB_10:
2000+
pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2001+
&pci_config_word);
2002+
pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2003+
pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2004+
pci_config_word);
2005+
break;
2006+
case 0x3c28: /* Xeon E5 1600/2600/4600 */
2007+
case 0x0e28: /* Xeon E5/E7 V2 */
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case 0x2f28: /* Xeon E5/E7 V3,V4 */
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case 0x6f28: /* Xeon D-1500 */
2010+
case 0x2034: /* Xeon Scalable Family */
2011+
pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2012+
&pci_config_dword);
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pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
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pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2015+
pci_config_dword);
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break;
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default:
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return;
2019+
}
19882020
pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
19892021
dev->vendor, dev->device);
19902022
}
1991-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1992-
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
2023+
/*
2024+
* Device 29 Func 5 Device IDs of IO-APIC
2025+
* containing ABAR—APIC1 Alternate Base Address Register
2026+
*/
2027+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2028+
quirk_disable_intel_boot_interrupt);
2029+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2030+
quirk_disable_intel_boot_interrupt);
2031+
2032+
/*
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* Device 5 Func 0 Device IDs of Core IO modules/hubs
2034+
* containing Coherent Interface Protocol Interrupt Control
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*
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* Device IDs obtained from volume 2 datasheets of commented
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* families above.
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*/
2039+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2040+
quirk_disable_intel_boot_interrupt);
2041+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2042+
quirk_disable_intel_boot_interrupt);
2043+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2044+
quirk_disable_intel_boot_interrupt);
2045+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2046+
quirk_disable_intel_boot_interrupt);
2047+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2048+
quirk_disable_intel_boot_interrupt);
2049+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2050+
quirk_disable_intel_boot_interrupt);
2051+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2052+
quirk_disable_intel_boot_interrupt);
2053+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2054+
quirk_disable_intel_boot_interrupt);
2055+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2056+
quirk_disable_intel_boot_interrupt);
2057+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2058+
quirk_disable_intel_boot_interrupt);
19932059

19942060
/* Disable boot interrupts on HT-1000 */
19952061
#define BC_HT1000_FEATURE_REG 0x64

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