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perf: Add MergeOrdered IR node with proper sim interleaving hooks#2828

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Benjscho wants to merge 3 commits intohydro-project:mainfrom
Benjscho:merge_ordered_sim
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perf: Add MergeOrdered IR node with proper sim interleaving hooks#2828
Benjscho wants to merge 3 commits intohydro-project:mainfrom
Benjscho:merge_ordered_sim

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Addresses #2768

Replace the sliced!-based merge_ordered implementation with a dedicated HydroNode::MergeOrdered IR node that has distinct codegen for production and simulation.

Production codegen:

  • Emits union() DFIR operator (both inputs pulled in same stratum)

Simulation codegen (two modes):

  • Bounded/tick: MergeOrderedHook (inline) buffers both batches and generates a valid interleaving via boolean coin flips, preserving per-input order. Explores C(a+b, a) states instead of (a+b)!.
  • Unbounded/top-level: TopLevelMergeOrderedHook releases one element at a time from the front of either input queue, allowing feedback cycles to deliver elements between releases.

API changes:

  • Removed NoTick bound from merge_ordered — works on any Location and Boundedness now. When bounded, the nondet is still explored in sim.
  • State space reduced from 26 to 6 instances in the existing test (2 elements per input: C(4,2) = 6 valid interleavings).

Tests added:

  • sim_merge_ordered: ordering preservation assertion (invalid interleavings like [2,1,3,4] are never produced)
  • sim_merge_ordered_one_empty: pass-through when one input is empty
  • sim_merge_ordered_cycle_back: feedback cycle where a cycled-back element arrives before elements on the other input
  • sim_merge_ordered_delayed: delayed element on one input
  • deploy_merge_ordered_delayed: production localhost test with timing

@Benjscho Benjscho requested a review from a team April 30, 2026 22:28
@Benjscho Benjscho force-pushed the merge_ordered_sim branch from 0ced1e2 to 2f1cd7c Compare April 30, 2026 23:44
@Benjscho Benjscho changed the title Add MergeOrdered IR node with proper sim interleaving hooks perf: Add MergeOrdered IR node with proper sim interleaving hooks Apr 30, 2026
Addresses hydro-project#2768

Replace the sliced!-based merge_ordered implementation with a dedicated
HydroNode::MergeOrdered IR node that has distinct codegen for production
and simulation.

Production codegen:
- Emits union() DFIR operator (both inputs pulled in same stratum)

Simulation codegen (two modes):
- Bounded/tick: MergeOrderedHook (inline) buffers both batches and
  generates a valid interleaving via boolean coin flips, preserving
  per-input order. Explores C(a+b, a) states instead of (a+b)!.
- Unbounded/top-level: TopLevelMergeOrderedHook releases one element
  at a time from the front of either input queue, allowing feedback
  cycles to deliver elements between releases.

API changes:
- Removed NoTick bound from merge_ordered — works on any Location and
  Boundedness now. When bounded, the nondet is still explored in sim.
- State space reduced from 26 to 6 instances in the existing test
  (2 elements per input: C(4,2) = 6 valid interleavings).

Tests added:
- sim_merge_ordered: ordering preservation assertion (invalid
  interleavings like [2,1,3,4] are never produced)
- sim_merge_ordered_one_empty: pass-through when one input is empty
- sim_merge_ordered_cycle_back: feedback cycle where a cycled-back
  element arrives before elements on the other input
- sim_merge_ordered_delayed: delayed element on one input
- deploy_merge_ordered_delayed: production localhost test with timing
@Benjscho Benjscho force-pushed the merge_ordered_sim branch from 2f1cd7c to d1316fc Compare April 30, 2026 23:51
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